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| integrated silicon solution, inc. ? 1-800-379-4774 1 rev. a 12/01/2003 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? internal self-timed write cycle individual byte write control and global write clock controlled, registered address, data and control linear burst sequence control using mode input three chip enable option for simple depth expansion and address pipelining common data inputs and data outputs jedec 100-pin tqfp package single +3.3v, +10%, ?5% power supply power-down snooze mode single cycle deselect snooze mode for reduced-power standby t version (three chip selects) d version (two chip selects) description the issi is61sps25632, is61sps25636, and is61sps51218 are high-speed, low-power synchronous static rams de- signed to provide a burstable, high-perfor mance memory for communication and networking applications. the is61sps25632 is organized as 262,144 words by 32 bits and the is61sps25636 is organized as 262,144 words by 36 bits. the is61sps51218 is organized as 524,288 words by 18 bits. fabricated with issi 's advanced cmos technology, the device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs i nto a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be from one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. byte write operation is performed by using byte write enable (bwe) input combined with one or more individual byte write signals ( bwx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating. 256k x 32, 256k x 36, 512k x 18 synchronous pipeline, single-cycle deselect static ram december 2003 fast access time symbol parameter -133 units t kq clock access time 4ns t kc cycle time 7.5 ns frequency 133 mhz
2 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? block diagram 18/19 binary counter a17-a0 (61sps25632/36 ) bwa gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 16/17 18/19 address register ce d clk q dqd byte write registers d clk q dqc byte write registers d clk q dqb byte write registers d clk q dqa byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bwd (t, d) ce (t) ce2 (t, d) ce2 bwb bwc 256kx32; 256kx36; 512kx18 memory array 32, 36, or 18 input registers clk output registers clk oe 4 oe dqa - dqd 32, 36, or 18 32, 36, or 18 a18-a0 (61sps51218 ) (x32/x36) (x32/x36/x18) (x32/x36) (x32/x36/x18) integrated silicon solution, inc. ? 1-800-379-4774 3 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? pin configuration nc dqb8 dqb7 vddq gnd dqb6 dqb5 dqb4 dqb3 gnd vddq dqb2 dqb1 gnd nc vdd zz dqa8 dqa7 vddq gnd dqa6 dqa5 dqa4 dqa3 gnd vddq dqa2 dqa1 nc a6 a7 ce ce2 bwd bwc bwb bwa a17 vdd gnd clk gw bwe oe adsc adsp adv a8 a9 nc dqc1 dqc2 vddq gnd dqc3 dqc4 dqc5 dqc6 gnd vddq dqc7 dqc8 nc vdd nc gnd dqd1 dqd2 vddq gnd dqd3 dqd4 dqd5 dqd6 gnd vddq dqd7 dqd8 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vdd nc nc a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 100-pin tqfp (d version) 256k x 32 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v zz snooze enable gnd q isolated output buffer ground 4 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? pin configuration nc dqb8 dqb7 vddq gnd dqb6 dqb5 dqb4 dqb3 gnd vddq dqb2 dqb1 gnd nc vdd zz dqa8 dqa7 vddq gnd dqa6 dqa5 dqa4 dqa3 gnd vddq dqa2 dqa1 nc a6 a7 ce ce2 bwd bwc bwb bwa ce2 vdd gnd clk gw bwe oe ads c adsp adv a8 a9 nc dqc1 dqc2 vddq gnd dqc3 dqc4 dqc5 dqc6 gnd vddq dqc7 dqc8 nc vdd nc gnd dqd1 dqd2 vddq gnd dqd3 dqd4 dqd5 dqd6 gnd vddq dqd7 dqd8 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vdd nc a17 a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 100-pin tqfp (t version) 256k x 32 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode bu rst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v zz snooze enable gnd q isolated output buffer ground integrated silicon solution, inc. ? 1-800-379-4774 5 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? pin configuration dqpb dqb8 dqb7 vddq gnd dqb6 dqb5 dqb4 dqb3 gnd vddq dqb2 dqb1 gnd nc vdd zz dqa8 dqa7 vddq gnd dqa6 dqa5 dqa4 dqa3 gnd vddq dqa2 dqa1 dqpa a6 a7 ce ce2 bwd bwc bwb bwa a17 vdd gnd clk gw bwe oe ads c adsp adv a8 a9 dqpc dqc1 dqc2 vddq gnd dqc3 dqc4 dqc5 dqc6 gnd vddq dqc7 dqc8 nc vdd nc gnd dqd1 dqd2 vddq gnd dqd3 dqd4 dqd5 dqd6 gnd vddq dqd7 dqd8 dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vdd nc nc a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 256k x 36 100-pin tqfp (d version) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v zz snooze enable dqpa-dqpd parity data i/o 6 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? pin configuration dqpb dqb8 dqb7 vddq gnd dqb6 dqb5 dqb4 dqb3 gnd vddq dqb2 dqb1 gnd nc vdd zz dqa8 dqa7 vddq gnd dqa6 dqa5 dqa4 dqa3 gnd vddq dqa2 dqa1 dqpa a6 a7 ce ce2 bwd bwc bwb bwa ce2 vdd gnd clk gw bwe oe adsc adsp adv a8 a9 dqpc dqc1 dqc2 vddq gnd dqc3 dqc4 dqc5 dqc6 gnd vddq dqc7 dqc8 nc vdd nc gnd dqd1 dqd2 vddq gnd dqd3 dqd4 dqd5 dqd6 gnd vddq dqd7 dqd8 dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vdd nc a17 a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 256k x 36 100-pin tqfp (t version) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode bu rst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v zz snooze enable dqpa-dqpd parity data i/o integrated silicon solution, inc. ? 1-800-379-4774 7 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a18 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwb synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqb synchronous data input/output mode burst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v zz snooze enable dqpa-dqpb parity data i/o dqpa is parity for dqa1-8; dqpb is parity for dqb1-8 pin configuration a17 nc nc vddq gnd nc dqpa dqa8 dqa7 gnd vddq dqa6 dqa5 gnd nc vdd zz dqa4 dqa3 vddq gnd dqa2 dqa1 nc nc gnd vddq nc nc nc a6 a7 ce ce2 nc nc bwb bwa ce2 vdd gnd clk gw bwe oe adsc adsp adv a8 a9 nc nc nc vddq gnd nc nc dqb1 dqb2 gnd vddq dqb3 dqb4 vdd vdd nc gnd dqb5 dqb6 vddq gnd dqb7 dqb8 dqpb nc gnd vddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vdd nc a18 a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 512k x 18 100-pin tqfp (t version) 8 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? partial truth table function gw gw gw gw gw bwe bwe bwe bwe bwe bwa bwa bwa bwa bwa bwb bwb bwb bwb bwb bwc bwc bwc bwc bwc bwd bwd bwd bwd bwd read h h xxxx read h l hhhh write byte 1 h l l h h h write all bytes h lllll write all bytes l xxxxx truth table address operation used ce ce ce ce ce ce2 ce2 ce2 ce2 ce2 ce2 adsp adsp adsp adsp adsp adsc adsc adsc adsc adsc adv adv adv adv adv write write write write write oe oe oe oe oe dq deselected, power-down none h x x x l x x x high-z deselected, power-down none l x h l xxxx high-z deselected, power-down none l l x l xxxx high-z deselected, power-down none l x h h l x x x high-z deselected, power-down none l l x h l x x x high-z read cycle, begin burst external l h l l xxxxq read cycle, begin burst external l h l h l x read x q write cycle, begin burst external l h l h l x w rite x d read cycle, continue burst next x x x h h l read l q read cycle, continue burst next x x x h h l read h high-z read cycle, continue burst next h x x x h l read l q read cycle, continue burst next h x x x h l read h high-z write cycle, continue burst next x x x h h l write x d write cycle, continue burst next h x x x h l write x d read cycle, suspend burst current x x x h h h read l q read cycle, suspend burst current x x x h h h read h high-z read cycle, suspend burst current h x x x h h read l q read cycle, suspend burst current h x x x h h read h high-z write cycle, suspend burst current x x x h h h w rite x d write cycle, suspend burst current h x x x h h w rite x d integrated silicon solution, inc. ? 1-800-379-4774 9 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? interleaved burst address table (mode = v dd or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) absolute maximum ratings (1) symbol parameter value unit t stg storage temperature ?55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ?0.5 to v ddq + 0.5 v v in voltage relative to gnd for ?0.5 to v dd + 0.5 v for address and control inputs v dd voltage on v dd supply relative to gnd ?0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1 10 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? operating range range ambient temperature v dd /v ddq commercial 0c to +70c 3.3v, +10%, ?5% industrial ?40c to +85c 3.3v, +10%, ?5% dc electrical characteristics (1) (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage i oh = ?4.0 ma, v ddq = 3.3v 2.4 ? v v ol output low voltage i ol = 8.0 ma, v ddq = 3.3v ? 0.4 v v ih input high voltage v ddq = 3.3v 2.0 v ddq + 0.3 v v il input low voltage v ddq = 3.3v ?0.3 0.8 v i li input leakage current gnd v in v ddq (2) com. ?2 2 a ind. ?5 5 i lo output leakage current gnd v out v ddq , oe = v ih com. ?2 2 a ind. ?5 5 power supply characteristics (over operating range) -133 symbol parameter test conditions max. unit i cc ac operating device selected, com. 230 ma supply current all inputs = v il or v ih ind. 250 ma oe = v ih , v dd = max. cycle time t kc min. i sb standby current device deselected, com. 40 ma v dd = max., ind. 50 ma all inputs = v ih or v il clk cycle time t kc min. notes: 1. the mode pin has an internal pullup. this pin may be a no connect, tied to gnd, or tied to v dd . 2. the mode pin should be tied to v dd or gnd. it exhibits 10 a maximum leakage current when tied to gnd + 0.2v or v dd ? 0.2v. integrated silicon solution, inc. ? 1-800-379-4774 11 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v for 3.3v i/o and reference level output load see figures 1 and 2 figure 2 317 ? 5 pf including jig and scope 351 ? output 3.3v for 3.3v i/o figure 1 output buffer z o = 50 ? 1.5v for 3.3v i/o 50 ? ac test loads 12 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? read/write cycle switching characteristics (over operating range) -133 symbol parameter min. max. unit f max clock frequency ? 133 mhz t kc cycle time 7.5 ? ns t kh clock high pulse width 2.8 ? ns t kl clock low pulse width 2.8 ? ns t kq clock access time ? 4 ns t kqx (1) clock high to output invalid 1.5 ? ns t kqlz (1,2) clock high to output low-z 0 ? ns t kqhz (1,2) clock high to output high-z ? 4 ns t oeq output enable to output valid ? 4 ns t oelz (1,2) output enable to output low-z 0 ? ns t oehz (1,2) output enable to output high-z ? 4 ns t as address setup time 1.5 ? ns t ss address status setup time 1.5 ? ns t ws write setup time 1.5 ? ns t ces chip enable setup time 1.5 ? ns t avs address advance setup time 1.5 ? ns t ah address hold time 0.5 ? ns t sh address status hold time 0.5 ? ns t wh write hold time 0.5 ? ns t ceh chip enable hold time 0.5 ? ns t avh address advance hold time 0.5 ? ns note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2. integrated silicon solution, inc. ? 1-800-379-4774 13 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? write cycle switching characteristics (over operating range) -133 symbol parameter min. max. unit t kc cycle time 7.5 ? ns t kh clock high pulse width 2.8 ? ns t kl clock low pulse width 2.8 ? ns t as address setup time 1.5 ? ns t ss address status setup time 1.5 ? ns t ws write setup time 1.5 ? ns t ds data in setup time 1.5 ? ns t ces chip enable setup time 1.5 ? ns t avs address advance setup time 1.5 ? ns t ah address hold time 0.5 ? ns t sh address status hold time 0.5 ? ns t dh data in hold time 0.5 ? ns t wh write hold time 0.5 ? ns t ceh chip enable hold time 0.5 ? ns t avh address advance hold time 0.5 ? ns snooze mode electrical characteristics symbol parameter conditions mi n. max. unit i sb 2 current during snooze mode zz vih ? 15 ma t pds zz active to input ignored ? 2 cycle t pus zz inactive to input sampled 2 ? cycle t zzi zz active to snooze current ? 2 cycle t rzzi zz inactive to exit snooze current 0 ? ns 14 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? read/write cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bwx bwe gw address adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst pipelined read 2a 2b integrated silicon solution, inc. ? 1-800-379-4774 15 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? write cycle timing single write data out data in oe ce2 ce2 ce bwx bwe gw address adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2a 2b 16 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? snooze mode timing don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z integrated silicon solution, inc. ? 1-800-379-4774 17 rev. a 12/01/03 is61sps25632t/d is61sps25636t/d is61sps51218t issi ? commercial range: 0c to +70c speed order part number package 133 mhz is61sps51218t-133tq tqfp industrial range: ?40c to +85c speed order part number package 133 mhz is61sps51218t-133tqi tqfp ordering information commercial range: 0c to +70c speed order part number package 133 mhz is61sps25632t-133tq tqfp is61sps25632d-133tq tqfp industrial range: ?40c to +85c speed order part number package 133 mhz is61sps25632t-133tqi tqfp commercial range: 0c to +70c speed order part number package 133 mhz is61sps25636t-133tq tqfp IS61SPS25636D-133TQ tqfp industrial range: ?40c to +85c speed order part number package 133 mhz is61sps25636t-133tqi tqfp integrated silicon solution, inc. ? 1-800-379-4774 packaging information issi ? pk13197lq rev. d 05/08/03 tqfp (thin quad flat pack package) package code: tq thin quad flat pack (tq) millimeters inches millimeters inches symbol min max min max min max min max ref. std. no. leads (n) 100 128 a ? 1.60 ? 0.063 ? 1.60 ? 0.063 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 0.17 0.27 0.007 0.011 d 21.90 22.10 0.862 0.870 21.80 22.20 0.858 0.874 d1 19.90 20.10 0.783 0.791 19.90 20.10 0.783 0.791 e 15.90 16.10 0.626 0.634 15.80 16.20 0.622 0.638 e1 13.90 14.10 0.547 0.555 13.90 14.10 0.547 0.555 e 0.65 bsc 0.026 bsc 0.50 bsc 0.020 bsc l 0.45 0.75 0.018 0.030 0.45 0.75 0.018 0.030 l1 1.00 ref. 0.039 ref. 1.00 ref. 0.039 ref. c0 o 7 o 0 o 7 o 0 o 7 o 0 o 7 o notes: 1. all dimensioning and tolerancing conforms to ansi y14.5m-1982. 2. dimensions d1 and e1 do not include mold protrusions. allowable protrusion is 0.25 mm per side. d1 and e1 do include mold mismatch and are determined at datum plane -h-. 3. controlling dimension: millimeters. d d1 e e1 1 n a2 a a1 e b seating plane c l1 l |
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